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Physical Design Engineer - Full-Chip Timing
Location:
Austin, TX
Description:
Job Description Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Who We Are Become a key member of a team participating in the Integration and Verification of a future Intel CPU. This position requires an Engineer with broad Physical Design and Static Timing Analysis skills, coupled with the leadership skills necessary to drive methodology and to collaborate effectively with multiple functional teams within the CPU design team. Who You Are We are looking for a highly motivated and technically savvy experienced engineer to drive the timing convergence for Full-Chip models.Responsibilities may include but not limited to: As a Full Chip Design Engineer, you will perform constraints management and STA verification. You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR. You will drive timing closure and provide collateral for SOC drops. Behavior skills we are looking for: Excellent written and oral presentation skills, and willing to work across multiple organizations and geographies. Effective team player with continuous learning mindset. Strong analytical and problem-solving skills. Be willing to balance multiple tasks. Self-starter with a collaborative spirit, comfortable asking for help when needed. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Possess Bachelor's degree in Electrical Engineering, Computer Engineering or similar field with 3+ years of relevant experience or MS degree in Electrical Engineering, Computer Engineering or similar field with 1+ years of relevant experience. Experience with Static Timing Analysis using PrimeTime Experience with Scripting in one or more of the following languages (TCL, Perl, or Python) Preferred Qualifications: Experience with verification of power crossing ie. VC-static (VC LP), UPF Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0260673pca3lyuhf
Company:
Intel
Posted:
May 10 on ITJobsWeb
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More About this Listing: Physical Design Engineer - Full-Chip Timing
Physical Design Engineer - Full-Chip Timing is a Engineering Design Engineer Job at Intel located in Austin TX. Find other listings like Physical Design Engineer - Full-Chip Timing by searching Oodle for Engineering Design Engineer Jobs.
Physical Design Engineer - Full-Chip Timing is a Engineering Design Engineer Job at Intel located in Austin TX. Find other listings like Physical Design Engineer - Full-Chip Timing by searching Oodle for Engineering Design Engineer Jobs.