Physical Verification Engineer (Parasitic Extraction)

This listing was posted on ITJobsWeb.

Physical Verification Engineer (Parasitic Extraction)

Location:

Phoenix, AZ

Description:

Job Description Designs, develops, tests, and debugs software tools, flows, and methodologies used in design automation and by teams in the design of hardware products, process design, or manufacturing. Responsibilities include capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or performing unit, integration, and endtoend testing of the software tools. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate must possess an MS degree with 2+ years of experience in Electrical Engineering, Computer Engineering, Material Sciences, or related field. 2+ years of experience in the following: - Semiconductor Device Physics. - Synopsys StarRC, ICV OR Cadence Quantus (QRC) OR Siemens - Xact, Calibre - Virtuoso Custom Layout. Preferred Qualifications: 1+ years of experience in the following: - Synopsys HSPICE. - Python or Perl for Automation Validation. - Validation experience on semiconductor EDA tools and PDK. #Designenablement Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. Other Locations US, OR, Hillsboro; US, CA, San Jose Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $106,231.00-$159,109.00*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0263006pca3lyuhf

Company:

Intel

Posted:

April 26 on ITJobsWeb

Visit Our Partner Website

This listing was posted on another website. Click here to open: Go to ITJobsWeb

Important Safety Tips

Always meet the employer in person.
Avoid sharing sensitive personal and financial information.
Avoid employment offers that require a deposit or investment.

To learn more, visit the Safety Center or click here to report this listing.

Physical Verification Engineer (Parasitic Extraction) | Engineer in Engineering Job at Intel in Ph1

Physical Verification Engineer (Parasitic Extraction)

Visit Our Partner Website